Hey Guys,
I am having a problem making a simple positive-edge-triggered D flip-flop circuit. I have double checked the wiring and logic and it all seems to be correct. The problem is that the output seems to change every time I power on the circuit. I was wondering if someone could explain why? If you swap out the bit that is constantly 0 with a clock the circuit behaves as expected. I have included a png and zip file of my circuit.
Cheers
Skyaxe
flip flop bug?
flip flop bug?
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Re: flip flop bug?
Hi Skyaxe,
The circuit has one problem. The wire in the left upper corner is not connected to any connection point but rather just floating and only touching the side of the NAND gate.
It is fairly simple to detect such kind mistakes. You need to power off the circuit and click menu Edit/Select Free Wires or Edit/Select Floating Symbols. This will select wires and symbols that are not connected.
However this will not change randomness during powering up. This is because the initial state of the flip flop depends on which of the gates is faster. So there is a race between them and whoever wins will have a precedence to set up the flip flop state. Please note that the same is happening in the real circuits.
In order to have predictable behavior you need to have something like "reset" input on the flip flop and send initiate signal after your circuit get powered. Please have a look at this article:
http://www.logiccircuit.org/forum/viewtopic.php?f=3&t=3
It explains how to detect power up and reset your circuits.
Thanks,
Eugene
The circuit has one problem. The wire in the left upper corner is not connected to any connection point but rather just floating and only touching the side of the NAND gate.
It is fairly simple to detect such kind mistakes. You need to power off the circuit and click menu Edit/Select Free Wires or Edit/Select Floating Symbols. This will select wires and symbols that are not connected.
However this will not change randomness during powering up. This is because the initial state of the flip flop depends on which of the gates is faster. So there is a race between them and whoever wins will have a precedence to set up the flip flop state. Please note that the same is happening in the real circuits.
In order to have predictable behavior you need to have something like "reset" input on the flip flop and send initiate signal after your circuit get powered. Please have a look at this article:
http://www.logiccircuit.org/forum/viewtopic.php?f=3&t=3
It explains how to detect power up and reset your circuits.
Thanks,
Eugene
Re: flip flop bug?
Hi,
Where is your primary output in this circuit? If it is in the middle the connection of your 2 NAND GATES must be interchange that's why your output seems changing everytime you power up your circuit. Just connect it before the another 2 NAND GATES in the middle and your problem will be solve.
Regards
china turnkey assembly
Where is your primary output in this circuit? If it is in the middle the connection of your 2 NAND GATES must be interchange that's why your output seems changing everytime you power up your circuit. Just connect it before the another 2 NAND GATES in the middle and your problem will be solve.
Regards
china turnkey assembly