logic question-- 2 Clocks, 1 SPDT

[JOHNYRADIO]

Hello

I've got a SPDT switch, S1.
And a clock C1. Every time the C1 goes High, it should drive S1 high (switch to position 1).
There's a slower clock, C2. When C2 goes High, it should drive S1 low (switch to position 2).
If C1 and C2 go high at the same time, C2 wins.

How to do this?

Thank You.

[admin]

I am not quite understood what you mean. I guess for starter you need to think about truth table for you circuit.
If I am getting you task correctly you probably have something like:

C1 |C2 | S1
0 | 0 | 0
1 | 0 | 1
0 | 1 | 0
1 | 1 | 0

Then you circuit needs to implement the following logic:
C1 & !C2

[JOHNYRADIO]

Here's a solution that was suggested to me.


Here's my version of the same circuit. (note, the D's are not part of the solution, they are use to generate C2):


It seems like a great idea. But as you can see from the trace (below), the output is not going high and low as desired. I need Q to go high on the first C1 rise after the first C2 rise, as described in the OP.

another issue with this solution is, i'm seeing rises in the output on C1 falls, which is not desired. All changes should happen only on rising edges....



i have struggled with numerous truth tables, but just cannot get it! One of my truth tables suggests that driving both clocks through an AND gate may be the solution, but i can't get anything working with that either.



any ideas?

thank you!