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Well, the problem is synchronization of your circuit.
First, your flip-flops are not raising edge triggering they are level triggering. To fix it I’ve changed it to rear edge triggering. But it turns out not enough too, I also AND the output of comparator with clock. Now it appears to be working.

Can you share your project file? It is hard to see what is going on from just a picture.

Thanks for the suggestion. This is indeed much better way to get the reset signal.

Can you be more specific? What exactly you need to do?

Every cell is still has only 4 connections, right?
Implementing variable bit with gates will be quite confusing. I've already heard a few different ideas from people on how it should work. Which leads me to understanding that current implementation is the clearest.

I don't see any attachments. Did you delete them all?

I guess the error is pretty self-explanatory. You have connected two pins with different bit width. One is one bit pin and another is 4 bit pin.
Just make them the same.

As I mentioned first replace all your flip-flops with just one, then make it working on rear front.
I guess you can look master-slave diagram here:
https://www.electronics-tutorials.ws/se ... seq_2.html

The problem is on both of your Mod 10 and Mod 6 counters as well as on JK flip-flop your input pin CLK are connected to it's actual input as well as clock on the circuit itself. The easiest way to fix is just remove clock on both counters and JK. However, after you fix it, you will see oscillation e...

Hi,
It is very hard to say where the error is by looking at the pictures. Can you please attach your project file?